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74VHC161 4-Bit Binary Counter with Asynchronous Clear
August 1993 Revised February 2002
74VHC161 4-Bit Binary Counter with Asynchronous Clear
General Description
The VHC161 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC161 is a high-speed synchronous modulo16 binary counter. This device is synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The VHC161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.
Features
s High Speed: fMAX = 185 MHz (typ) at TA = 25C s Synchronous counting and loading s High-speed synchronous expansion s Low power dissipation: ICC = 4 A (max) at TA = 25C s High noise immunity: VNIH = VNIL = 28% VCC (min) s Power down protection provided on all inputs s Low noise: VOLP = 0.8V (max) s Pin and function compatible with 74HC161
Ordering Code:
Order Number 74VHC161M 74VHC161SJ 74VHC161MTC 74VHC161N Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
(c) 2002 Fairchild Semiconductor Corporation
DS011635
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74VHC161
Connection Diagram
Pin Descriptions
Pin Names CEP CET CP MR P0-P3 PE Q0-Q3 TC Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Asynchronous Master Reset Input Parallel Data Inputs Parallel Enable Inputs Flip-Flop Outputs Terminal Count Output
Functional Description
The VHC161 counts in modulo-16 binary sequence. From state 15 (HHHH) it increments to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the VHC161) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset, parallel load, count-up and hold. Five control inputs--Master Reset, Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)--determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The VHC161 uses D-type edge-triggered flip-flops and changing the PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min to start its final cycle. Since this final cycle requires 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. Logic Equations: Count Enable = CEP * CET * PE TC = Q0 * Q1 * Q2 * Q3 * CET
FIGURE 1. Multistage Counter with Ripple Carry
FIGURE 2. Multistage Counter with Lookahead Carry
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74VHC161
State Diagram Mode Select Table
Action on the Rising PE MR L H H H H X L H H H X X H L X X X H X L CET CEP Clock Edge () Reset (Clear) Load (PnQn) Count (Increment) No Change (Hold) No Change (Hold)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VHC161
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260C
-0.5V to +7.0V -0.5V to +7.0V -0.5V to VCC + 0.5V -20 mA 20 mA 25 mA 50 mA -65C to +150C
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC = 3.3V 0.3V VCC = 5.0V 0.5V 0 100 ns/V 0 20 ns/V 2.0V to +5.5V 0V to +5.5V 0V to VCC
-40C to +85C
Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0 - 5.5 2.0 3.0 - 5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IIN ICC Input Leakage Current Quiescent Supply Current 0 - 5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 4.0 2.0 3.0 4.5 TA = 25C Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 1.0 40.0 V A A V VIN = VIH or VIL IOL = 4 mA IOL = 8 mA VIN = 5.5V or GND VIN = VCC or GND IOL = 50 A V V VIN = VIH or VIL IOH = -4 mA IOH = -8 mA IOH = -50 A Typ Max TA = -40C to +85C Min 1.50 0.7 VCC 0.50 0.3 VCC Max Units V V Conditions
Noise Characteristics
Symbol VOLP (Note 3) VOLV (Note 3) VIHD (Note 3) VILD (Note 3) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 TA = 25C Typ 0.4 -0.4 Limits 0.8 -0.8 3.5 1.5 Units V V V V CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF Conditions
Note 3: Parameter guaranteed by design.
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74VHC161
AC Electrical Characteristics
Symbol tPLH tPHL Parameter Propagation Delay Time (CP-Qn) VCC (V) 3.3 0.3 5.0 0.5 tPLH tPHL Propagation Delay Time (CP-TC, Count) 3.3 0.3 5.0 0.5 tPLH tPHL Propagation Delay Time (CP-TC, Load) 3.3 0.3 5.0 0.5 tPLH tPHL Propagation Delay Time (CET-TC) 3.3 0.3 5.0 0.5 tPHL Propagation Delay Time (MR -Qn) 3.3 0.3 5.0 0.5 tPHL Propagation Delay Time (MR -TC) 3.3 0.3 5.0 0.5 fMAX Maximum Clock Frequency 3.3 0.3 5.0 0.5 CIN CPD Input Capacitance Power Dissipation Capacitance 80 55 135 95 Min TA = 25C Typ 8.3 10.8 4.9 6.4 8.7 11.2 4.9 6.4 11.0 13.5 6.2 7.7 7.5 10.5 4.9 6.4 8.9 11.2 5.5 7.0 8.4 10.9 5.0 6.5 130 85 185 125 4 23 10 Max 12.8 16.3 8.1 10.1 13.6 17.1 8.1 10.1 17.2 20.7 10.3 12.3 12.3 15.8 8.1 10.1 13.6 17.1 9.0 11.0 13.2 16.7 8.6 10.6 TA = -40 to +85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 70 50 115 85 10 Max 15.0 18.5 9.5 11.5 16.0 19.5 9.5 11.5 20.0 23.5 12.0 14.0 14.5 18.0 9.5 11.5 16.0 19.5 10.5 12.5 15.5 19.0 10.0 12.0 Units ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz pF pF Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF VCC = Open (Note 4)
Note 4: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD * VCC * fIN + ICC. When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ICC which is obtained from the following formula:
CQ0-C Q3 and CTC are the capacitances at Q0-Q3 and TC, respectively. F CP is the input frequency of the CP.
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74VHC161
AC Operating Requirements
Symbol tS tS tS tH tH tH tW(L) tW(H) tW(L) tREC Parameter Minimum Setup Time (Pn-CP) Minimum Setup Time (PE -CP) Minimum Setup Time (CEP or CET-CP) Minimum Hold Time (Pn-CP) Minimum Hold Time (PE -CP) Minimum Hold Time (CEP or CET-CP) Minimum Pulse Width CP (Count) Minimum Pulse Width (MR) Minimum Removal Time
Note 5: VCC is 3.3 0.3V or 5.0 0.5V
VCC (Note 5) (V) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
TA = 25C Typ
TA = -40C to +85C Guaranteed Minimum 5.5 4.5 8.0 5.0 7.5 5.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 5.0 5.0 5.0 2.5 1.5 6.5 4.5 9.5 6.0 9.0 6.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 5.0 5.0 5.0 2.5 1.5 Units
ns ns ns ns ns ns ns ns ns
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74VHC161
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
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74VHC161
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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74VHC161
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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74VHC161 4-Bit Binary Counter with Asynchronous Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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